1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to LD (Lateral Double Diffused) MOS transistor technology which is used for a high voltage element for e.g. liquid crystal driving IC.
2. Description of the Related Art
Now, an LDMOS transistor structure refers to a structure in which impurities with a different conduction type are diffused in a diffused region formed on surface of a semiconductor substrate to form another diffused region and a difference in the horizontal diffusion between these diffused regions is employed as an effective channel length. This structure, in which a short channel is formed, can constitute an element with low "on" resistance.
FIG. 10 is a sectional view for explaining a conventional LDMOS transistor which are being developed by the inventors of the invention. A N-channel LDMOS transistor structure is illustrated. Although the structure of a P-channel LDMOS transistor structure is not explained here, it is well known that the same structure can be adopted except for its conduction type.
In FIG. 10A, reference numeral 1 denotes a semiconductor substrate with a first conduction type, e.g. P-type, and reference numeral 21 denotes a P-type well region. A P-type body region 3 is formed within the P-type well region 21. An N-type diffused region 4 is formed within the P-type body region 3. Another N-type diffused region 5 is formed apart from the N-type diffused region 4. A gate electrode 7 is formed on the surface of the substrate 1 through a gate insulating film 6. A channel region 8 is formed in the surface region of the P-type body region 3 immediately below the gate electrode.
The N-type diffused region 4 is used as a source region whereas the N-type diffused region is used as a drain region. A drift region (N.sup.- layer 22) is formed which is composed of a shallow region (first N.sup.- layer 22A) below the gate electrode 7 and deep region (second N.sup.- layer 22B) in the vicinity of the drain region. Further, a source electrode and drain electrode (not shown) are formed on the surface so as to contact with source and drain region, respectively. A P-type diffused region 12 for assuming the potential of the P-type body region 3 is formed through an interlayer insulating film.
In the above LDMOS transistor, which has a high impurity concentration on the surface of the N-type drift region, a current is apt to flow in the surface of the N-type drift region, thereby realizing a high withstand voltage. The LDMOS transistor having such a configuration is referred to as a surface relax type (RESURF)LDMOS.
However, since the impurity concentration is high in the surface of the N-type drift region 22, the P-type body region 3 cannot diffuse sufficiently. Therefore, as shown in FIG. 10B, the edge of the P-type body region 3 approaches the source region (N-type diffused region 4) so that the channel region B may be not be formed to have a suitable size and impurity concentration(see indicated arrow).
The inventors of the invention tried to solve the above problem by rearranging the manufacturing steps and eventually completed the present invention. Specifically, in the conventional process, the drift region (N.sup.- layer 22) was formed in such a manner that at least two N-type impurities (phosphorus ions or arsenic ions) with different diffusion coefficients are ion-implanted and diffused in the surface layer of the P-type well region 21, and thereafter P-type impurities (boron ions) are ion-implanted and diffused into the surface layer of the P-type well region 21 where the source region is to be formed so that the boron ions thus diffused cancel the phosphorous ions of the second N.sup.- layer 22B (diffused layer originating from phosphorus ions) formed at a relatively deep position of the P-type well region of the source region.
However, the following fact was confirmed. The drift region (N.sup.- layer 22), after it has been formed, is subjected to thermal oxidation to form a gate insulating film 6. Therefore, arsenic ions contained in the first N.sup.- layer (with arsenicions diffused) are segregated on the substrate surface. Because of the segregated arsenic ions, the P-type body region does not diffuse sufficiently so that the channel region 8 cannot be formed to have a suitable size (see a hatched region showing segregated ions in the graph of FIG. 9).